![]() ![]() Ordering information Combines 3-to-8 decoder with 3-bit latch Multiple input enable for easy expansion or independent controls Active HIGH mutually exclusive outputs Low-power dissipation ESD protection: HBM JESD22-A114F exceeds V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to+85c and from 40 C to+125c Table 1. ![]() The is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. Further address changes are ignored as long as LE remains HIGH. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. When the latch is enabled (LE = LOW), the acts as a 3-to-8 active LOW decoder. The essentially combines the 3-to-8 decoder function with a 3-bit storage latch. The is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The is specified in compliance with JEDEC standard no. General description The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
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